1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to semiconductor devices that are compatible with multiple logic interfaces.
2. Description of the Related Art
Semiconductor devices having a plurality of memory devices and a plurality of array groups for the memory devices are interfaced to other components through more than one type of logic interface. For example, a synchronous dynamic random access memory device has two types of interfaces: low voltage transistor transistor logic (LVTTL) and stub series terminated transceiver logic (SSTL). The LVTTL is used for conventional dynamic random access memory, and the SSTL is used for synchronous dynamic random access memory. Differences between logic levels for the LVTTL and the SSTL interfaces are shown in Table 1.
TABLE 1 ______________________________________ items LVTTL SSTL ______________________________________ Vih/Vil 2.0V/0.8V (VREF + 0.2)V/(VREF - 0.2)V VOH/VOL 2.4V/0.4V (Vtt + 0.8)V/(Vtt - 0.8)V AC measurement point 1.4V Vtt VREF no application application from system ______________________________________
Some of the differences between LVTTL and SSTL interfaces will now be described in more detail. First, with SSTL, the input buffers utilize an external reference voltage VREF, but with LVTTL, the input buffers use an internally generated reference voltage. Second, LVTTL and SSTL have different input voltage swings. That is, Vih/Vil for LVTTL are 2.0V/0.8V, while Vih/Vil for SSTL are (VREF+0.2)V/(VREF-0.2)V. Thus, the input voltage swing is narrower for SSTL. Third, LVTTL and SSTL have different output voltage swings. VOH/VOL for LVTTL are 2.4V/0.4V DC, and the AC measurement point for the AC voltage level is 1.4V. However, VOH/VOL for SSTL is (Vtt+0.8)V/(Vtt-0.8)V at a DC voltage level based on a terminal voltage (Vtt), and the AC measurement point of the AC voltage level is the terminal voltage (Vtt).
In a synchronous semiconductor memory device, the SSTL interface is designed differently from the LVTTL in order to improve the performance thereof.
FIG. 1 is a block diagram of a conventional semiconductor device. Referring to FIG. 1, the conventional chip circuit is designed to be compatible with both LVTTL and SSTL interfaces. The device is configured for operation with either an LVTTL interface or an SSTL interface by using a hardwired bonding option during assembly of the device.
If the device is to be configured for operation with an SSTL interface, power/ground port 100 is connected to an SSTL pad 110 by a bonding wire during an assembly step so that an SSTL enable signal (PSSTL), which is generated by SSTL enable circuit 120, is activated (driven to a "thigh" logic level). The SSTL enable signal PSSTL causes SSTL dependent circuit 130 to operate so as to be compatible with an SSTL interface. Also, since the LVTTL interface uses the reference voltage generated by an internal reference voltage generator 170, and the SSTL interface uses an externally generated reference voltage that is applied via a reference voltage pad 140, the reference voltage pad 140 is bonded to an external pin when the device is configured for compatibility with an SSTL interface, and the SSTL enable signal causes the reference voltage control circuit 160 to block the internally generated reference voltage from the input buffer 150.
In contrast, when the device is configured for compatibility with an LVTTL interface, the power/ground port 100 is not bonded to the SSTL pad, and the VREF generated by the reference voltage generator 170 is applied to the input buffer 150 through reference voltage control circuit 160.
In the conventional semiconductor device shown in FIG. 1, a determination must be made during assembly as to which type of interface the device is to be configured for. Thus, the cost of manufacturing and distributing the device is increased if the respective market demands for the differently configured devices are not predicted accurately because devices configured for different interfaces are not compatible.
Accordingly, a need remains for an improved scheme for configuring semiconductor devices for compatibility with different logic interfaces.